sigma delta design problem

[zizi110]

Hi all,
i am trying to design a sigma delta modulator in pspice by ABM library , here it is my schematic , nut it dont work!
first block subtract the input from output , then the result goes to integrator and then if the result is positive the output becomes 5 , else the output becomes zero and this output goes to 74175 that its clock rate is 10kHz ..... however this circuit does not work!

any suggestion appreciated.

 

[FvM]

You forgot to tell which error you observed. It's also not clear how you derived the circuit parameters.

But at first sight, you implemented positive instaed of required negative feedback.

 

[zizi110]

Hi FvM ,thanks for your reply
i have a negative feedback in the loop; when i used (V(%IN1)-V(%IN2)) , it means subtract vin1( input signal) from vin2 (output of quantizer).
then it goes through low pass filter for filtering noise and then goes to integral unit ( it can be as simple as 1/S ) , then in the next block we said
if V(%IN) >0 then output=5 else output=0 ( it works like quantizer) , finally we have a latch block to set the sampling frequency at 10KHz.

can any one help me plz?