Should I ingore this DRC error(_M6T.E.1)?

[swgchlry]

I use cadence soc encounter & icfb to create a layout of a circuit with TSMC 0.18um process, but I got 1000+ _M6T.E.1 DRC errors in calibre. The errors info were listed as follows:
_M6T.E.1
1000 1000 3 Feb 25 20:17:35 2008
_M6T.E.1 { @ Min extension of a M6 region beyond a VIA5 region is 0.3 um
ENC VIA5 M6 < 0.3 ABUT<90 SINGULAR OVERLAP OUTSIDE ALSO
}

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What should I do with this error? Should I ingore this error?

 

[iwpia50s]

The error says you donot have sufficient metal 6 coverage over the via region. You can ignore it if you get a sign-off waver from your fab, but I think you fix it. Your via could be built wrong.

 

[moriar]

Ya fix it. Would be a pain if the metal fractures around the via. Open circuits etc. It shouldn't be a big problem to fix right? If it was due to routing tool, you may not have programmed the constraints properly. Or misalignment of your via.