ya, very interesting
from design of view, it's not possible to implement a current circuit into charge sharing memory cell.
cell of 1tsram is as same as dram structure.
if you try to using current sensing in this kind of cell, you got a big trouble. since current of this cell appears only in the moment of wl turns on. After charge sharing was done, no current can be detected. In the other words, voltage sensing should be introduce into ur design.
Moreover, dram like memory using folded layout style. adjacent cell using different word-line as select gate. So, reference is ur neighbor bit line.