Should false_path or max_delay be used to constrain synchronizers?

[ivlsi]

So, instead of setting false_path, should I define max_delay constraint? But how I tell to the tool to ignore metastability issues?

 

[ads-ee]

when using set_max_delay you add the switch set_max_delay -datapath_only to prevent the tools from timing from a launch clock to a destination clock. Using the set_max_dealy in this way ensures the path between the signal on the launch clock has a limited delay to reach the first synchronization FF.

 

[ivlsi]

Should I not to put set_false_path between clock domains while using the set_max_delay -datapath_only?

Will the set_max_delay -datapath_only command be ignored if I put set_false_path between clock domains?

 

[ads-ee]

Should I not to put set_false_path between clock domains while using the set_max_delay -datapath_only?

Will the set_max_delay -datapath_only command be ignored if I put set_false_path between clock domains?

Yes, set_false_path has higher priority so it will override the set_max_delay, which will then be ignored.

 

[ivlsi]

[Moved]What are Clock Groups?

Hi All,

What is "Clocks Group", when and why should they be used in STA?

I mean usage of set_clock_groups command.

Thank you!

 

[ivlsi]

[Moved]Difference between physically exclusive and logically exclusive clock groups ?

So, if the clock groups are defined as asynchronous then timing paths between these clock domains will be taken into consideration (calculated, checked, etc)?

Is there a reason to use set_false_path while using set_clock_group command?

 

[ivlsi]

[Moved]Difference between physically exclusive and logically exclusive clock groups ?

As for synchronizers, will it be correct to define logically exclusive clock groups and not to use set_false_path command?

 

[FvM]

In a brief, set_clock_group is the intelligent way of cutting timing pathes between unrelated clock domains.

There are good tutorials describing the Synopsys timing constraint syntax and answering your questions, e.g. the Altera Timquest User Guide by Ryan Scoville https://www.alterawiki.com/wiki/File:TimeQuest_User_Guide.pdf

 

[ivlsi]

So, as for the synchronizers, what constraints should be applied ?

1) set_clock_groups -logically_exclusive -group {clk1} -group {clk2}
2) set_max_delay -datapath_only -from FF1 -to FF2 {value}
Note: FF1 is driven by clk1, FF2 and FF3 are driven by clk2

What's else? No more setting false paths between synchronizers?

Thank you!