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when using set_max_delay you add the switch set_max_delay -datapath_only to prevent the tools from timing from a launch clock to a destination clock. Using the set_max_dealy in this way ensures the path between the signal on the launch clock has a limited delay to reach the first synchronization FF.
[Moved]Difference between physically exclusive and logically exclusive clock groups ?
So, if the clock groups are defined as asynchronous then timing paths between these clock domains will be taken into consideration (calculated, checked, etc)?
Is there a reason to use set_false_path while using set_clock_group command?
In a brief, set_clock_group is the intelligent way of cutting timing pathes between unrelated clock domains.
There are good tutorials describing the Synopsys timing constraint syntax and answering your questions, e.g. the Altera Timquest User Guide by Ryan Scoville
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