Shift Registers with Taps

[weilijun]

I am now working on a shift register. The shift register is defined as WxMxN, wherein W is the input data width, M is the distance between taps, and N is the total tap number. Alter QuartusII provides Megawizard function to implement such shift register using RAMs. Is there a counterpart for Xilinx ISE?

 

[Black Jack]

I am now working on a shift register. The shift register is defined as WxMxN, wherein W is the input data width, M is the distance between taps, and N is the total tap number. Alter QuartusII provides Megawizard function to implement such shift register using RAMs. Is there a counterpart for Xilinx ISE?

This simple task
Use HDL (VHDL or VERILOG)

ISE tools allow convert Altera projects
From Altera tools you need generate AHDL output file
and use it in ISE.

 

[weilijun]

Do you mean I should generate EDIF using Altera QuartusII and use this EDIF in ISE? If so, how can ISE implement it? Dose ISE use RAM or CLB to implement the shift register?
Thank you!

 

[bibo1978]

try SRL16E shift register, u can use the (A0,A1,A2 and A3) for the desired delay.

more details about it read it in the library guide "Xilinx library guide"

 

[williamgeorge]

Continuing its commitment of driving device performance and designer productivity, Altera Corporation (NASDAQ:ALTR) today announced the availability of Quartus II software version 9.0, the industry's leading CPLD, FPGA and HardCopy ASIC development environment. The 9.0 version includes full support for Altera's portfolio of transceiver FPGAs and HardCopy ASICs. Enhanced features within this latest Quartus II development environment ensure customers can deliver their Altera solutions to market sooner and with reduced engineering expenses.
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george
**broken link removed**