Every Flip-flop has setup/hold window around active clock edge. Setup before edge, hold after.
In shift registers data pass from Q-out of previous flop to D-in of the next flop directly, so it have minimal possible delay.
Data can pass to D-in inside hold window. To fix this violation you should put delay buffer from Q-out to D-in.
Another factor is clock skew. Clock to the next flop can arrive later than previous, co you need to put additional delay between Q and D.
Another way to fix hold violation is "useful skew" - delay clock to the previous flop relative to next flop.