hold violation shift register
I think you mean shift reg is for SCAN-DFF. When you do synthesis,
1. if between two clock domain , it will insert a latch to fix the data delay time.
2. And at shift scan chain , some hold time violation , synthesis tools can't deal with it, fix hold timing isn't synthesis work, and those will be fixed at backend.
Added after 17 minutes:
When we do a project , scan chain has a hold timing violation. Scan Cell working in same clock,
we will insert delay cell at backend. When do scan insert , synthesis tools just connect shift register, it will not optimaize timing of shift chain.