Shift-Register Design:Delay error

My Code
library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity b11 is
port(shin:in std_logic_vector(7 downto 0);
reset:in std_logic;
enable:in std_logic;
clock : in std_logic;
shoutut std_logic_vector(7 downto 0));
end b11;


architecture a of b11 is
begin

xulyrocess(clock,enable,reset)
begin
if reset ='1' then
shout<=(others=>'0');
elsif clock='1' and clock'event then
if enable='1' then
shout<=shin(3 downto 0)&"0000";
else
shout<=shin;
end if;
end if;
end process xuly;

end a;

My error
My output is delayed :when input is loaded at the rising of clock pulse and enable signal ='1' then output appear after one period
I'm sorry my English is not good

It's unclear what you want to achieve, the code is not describing a shift register. shout is loaded on each clock cycle, there's no "one period" delay. It may seem like this according to your test case.

This is my wave form

You are releasing reset simultaneously with the first clock edge, thus this edge is ignored.

I fixed it
thank you!