Shematics of Floating Gate MOS Inverter in Cadence.

[muffassir]

Hi all,

I want to draw and simulate the floating gate MOS inverter in virtuoso Cadence 615.Please refer the Circuit diagram attached.



I am using gpdk 180nm Virtuoso Schematics.In this i dont find any floating gate MOS symbol in the analog library and gpdk library...So please help me on how to draw the schematics and simulate the same....I am in urgent need of this since am going to do the project on it....The attached ckt diagram has floating gate MOS inverter wherein the floating gate is common to both the nmos and pmos...it will work even if they are different...

So please help me to draw the schematics and simulate it ...

Thanks in advance....

 

[erikl]

... draw the schematics and simulate the same...

Most important is to get a realistic Spice or Spectre simulation model. If you can get hold of such a model, creating an appropriate Virtuoso schematic, a schematic symbol and a simulation symbol shouldn't be a big problem.

 

[ducvilla]

I think it's not difficult to draw and simulate this circuit. You have to set Vdd, Vin, and Vc in the spice, then you will see the results. As erikl said: " the most important is to get a realistic spice or spectre simulation model", try it first.