[SOLVED] shared signals in Test Benches ?

[im&u]

Hi all,
I'm trying to write a test bench for a fpga as follows:

...
signal a : std_logic;--connected to input a of fpga
signal b : std_logic;--connected to input b of fpga
...
begin
...

main_tb_process: process
begin
--initialization
a <= '0';
b <= '0';

...
--command1
a <= '1';
...
end process

My question is:
is there any way that I can simplify the step of initialization by writing a procedure that when called resets all fpga inputs ? like this :

procedure init_fpga
begin
a <= '0';
b <= '0';
end procedure;

begin
...
main_tb_process: process
begin
--initialization
init_fpga;

...
--command1
a <= '1';
...
end process

The problem is that I want to keep control of signals a and b in the main process for command1 etc.

PS. I'm doing this because it may be useful when fpga has A LOT of inputs.

Thank you.

 

[aruipksni]

Hi all,
I'm trying to write a test bench for a fpga as follows:

...
signal a : std_logic;--connected to input a of fpga
signal b : std_logic;--connected to input b of fpga
...
begin
...

main_tb_process: process
begin
--initialization
a <= '0';
b <= '0';

...
--command1
a <= '1';
...
end process

My question is:
is there any way that I can simplify the step of initialization by writing a procedure that when called resets all fpga inputs ? like this :

procedure init_fpga
begin
a <= '0';
b <= '0';
end procedure;

begin
...
main_tb_process: process
begin
--initialization
init_fpga;

...
--command1
a <= '1';
...
end process

The problem is that I want to keep control of signals a and b in the main process for command1 etc.

PS. I'm doing this because it may be useful when fpga has A LOT of inputs.

Thank you.

The easy thing to do is to initialise signals when they are defined.
Signal mysignal : std_logic := `0';

 

[im&u]

The easy thing to do is to initialise signals when they are defined.
Signal mysignal : std_logic := `0';

Thank you for your reply.

That works if fpga needs to be initialized only once, but what about the case when I want to initialize those signals (init fpga) AGAIN after running some commands ?

like this :

main_tb_process: process
begin
--initialization
init_fpga;

...
--command1
a <= '1';
--check something
...
init_fpga;
--command2
...
end process

 

[TrickyDicky]

Thats perfectly fine, as long as init_fpga is only called from a single process - otherwise you'll have problems with multiple drivers.

- - - Updated - - -

you might be better off doing this, then you can connect any signals to it:

procedure init_fpga(x,y : out std_logic) is
begin
  x <= '0';
  y <= '0';
end procedure;


.....

init_fpga(a,b);
init_fpga(c,d);

--etc

 

[aruipksni]

It will work every time your fpga will be reconfigured and initilised. You can activate prog pin of fpga.of course if you dont want reconfigure youre fpga.then you will to conect all signal to some kind of reset logic. Another aproach will be to built a program that will analyse entire signals asigments and regenerate vhdl code.

 

[TrickyDicky]

It will work every time your fpga will be reconfigured and initilised. You can activate prog pin of fpga.of course if you dont want reconfigure youre fpga.then you will to conect all signal to some kind of reset logic. Another aproach will be to built a program that will analyse entire signals asigments and regenerate vhdl code.

What does this even mean?
This question is aimed only for a testbench, not an FPGA.

 

[K-J]

That works if fpga needs to be initialized only once, but what about the case when I want to initialize those signals (init fpga) AGAIN after running some commands ?

like this :

main_tb_process: process
begin
--initialization
init_fpga;

...
--command1
a <= '1';
--check something
...
init_fpga;
--command2
...
end process

It's not clear to me why this can't be in a single process. You can create the init_fpga procedure and call it from main_tb_process whenever you want. That would be the simplest way from what you've described.

However, if you really do want to drive them from seperate processes, then what you basically need to do is to create an arbiter. Then every process that wants to take control of that signal would request control of the signals from the arbiter process. Think of it as being the same way that you would if you were designing a shared bus multi-processor system.

Kevin Jennings

 

[im&u]

procedure init_fpga(x,y : out std_logic) is
begin
  x <= '0';
  y <= '0';
end procedure;


.....

init_fpga(a,b);
init_fpga(c,d);

--etc

Thank you all for your answers.

Is there any easier way to do that ?
I'm trying to shorten my test bench and this way I have to put all signal names in the list when calling init_fpga (it's not easy when fpga has many inputs (30 for example))

Also I have another question: is a wait statement in procedure always acceptable?
For example,
procedure init_fpga(x,y : out std_logic) is
begin
x <= '0';
wait for 10 ns;
y <= '0';
end procedure;

 

[TrickyDicky]

Then stick with the first option - no outputs and just modify the signals directly.
Yes you can use wait statements like that.

 

[im&u]

Then stick with the first option - no outputs and just modify the signals directly.
Yes you can use wait statements like that.

Now I see why it didn't work for me before (it's because I declared the procedure outside the main process where I call it and that's why I got this error "Cannot drive signal "..." from procedure)

Now it's working perfectly :

main_tb_process: process

procedure init_fpga
begin
a <= '0';
b <= '0';
end procedure;
​

begin
--initialization
init_fpga;

...

- - - Updated - - -

Thank you for your help !