sfixed compare not working [VHDL]

[priversek]

Hi

I am having trouble comparing two signed fixed point numbers in VHDL.
Below is code example.

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Code VHDL - [expand]
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signal kot : sfixed(2 downto -30);
signal delta_kot : sfixed(2 downto -30):="000000000000001111111111111111111";
constant half_pi : sfixed (2 downto -30) := to_sfixed(1.57,2,-30);
...
 
 if  ( (kot + delta_kot) > half_pi ) then
   max_reached <= '1';
   ...do something...
 else
   kot <= resize(kot + delta_kot, kot);
 end if;

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It looks like compare is not working correctly.
When synthesizing above code I get Warning: "Net <max_reached> does not have a driver."
What am I doing wrong?

I have also tried to cast the signals as signed() on both sides of compare, but then simulation is not working in modelsim, because I receive error: "index value -30 is out of std.standard.natural range 0 to 2147483647".
Please help, I am really stuck here...
Thanks

 

[TrickyDicky]

Thats a synthesis warning, meaning the synthesisor has determined that your code is useless and never occurs, and hence removed the max_reached branch.
is max_reached assigned anywhere else?
Does delta_kot ever get assigned anywhere?
are you sure it'ts not overflowing (your code allows values of -2 to +2- 2^-30)
You cannot cast the values directly to signed, because signed only allows +ve indeces (you need to use the to_signed conversion function instead).

Have you testbenched this code?

 

[priversek]

Thats a synthesis warning, meaning the synthesisor has determined that your code is useless and never occurs, and hence removed the max_reached branch.
is max_reached assigned anywhere else?
Does delta_kot ever get assigned anywhere?
are you sure it'ts not overflowing (your code allows values of -2 to +2- 2^-30)
You cannot cast the values directly to signed, because signed only allows +ve indeces (you need to use the to_signed conversion function instead).

Have you testbenched this code?

Ok, here is an example of VHDL code for more information regarding this problem (sfixed accumulator with compare).
I want to accumulate input a, until sum+a becomes grater than half_pi, then assert max_reached.

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library IEEE_PROPOSED;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
 
entity sfixed_compare is
    Port ( a : in sfixed(2 downto -30):="000000000000000000000000001000000";
         max_reached : out std_logic:='0';
            clk : in  std_logic        
           );
end sfixed_compare;
 
architecture Behavioral of sfixed_compare is
 
signal sum : sfixed(2 downto -30);
 
begin
 
compare_process: process(clk)  
 
constant half_pi : sfixed(2 downto -30):=to_sfixed(1.57,2,-30);
    
   begin
           
       if (rising_edge(clk)) then
          if resize(sum + a, sum) > half_pi  then
             max_reached <= '1';
          else
             sum <= resize(sum + a, sum);
          end if;
       end if;
 
    end process;
 
end Behavioral;

---

I receive this warnings when synthesizing above code:
WARNING:HDLCompiler:746 - "F:\le\xst\ieee_proposed\fixed_pkg_c.vhdl" Line 1470: Range is empty (null range)
WARNING:HDLCompiler:746 - "F:\le\xst\ieee_proposed\fixed_pkg_c.vhdl" Line 1471: Range is empty (null range)
WARNING:HDLCompiler:746 - "F:\le\xst\ieee_proposed\fixed_pkg_c.vhdl" Line 1472: Range is empty (null range)
WARNING:HDLCompiler:314 - "N:/M.53d/rtf/vhdl/xst/src/std_1164.vhd" Line 1025: Choice with meta-value 'U' is ignored for synthesis
WARNING:Xst:647 - Input <a<2:-30>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'max_reached', unconnected in block 'sfixed_compare', is tied to its initial value (0).

 

[TrickyDicky]

Warnings 1,2 and 3 relate to the fixed packages, and are deliberate (you cannot fix them, or at least you should not).
Warnings 4 also ignore.

Is A actually connected to a external signal, or have you just left it unconnected?

Well, max_reached is never set to anything other than '1', so it has no logic in it. If you want it to latch (like you appear to do) you need to give it an initial value or reset value (via a reset).
Also Sum has no initial or reset value.