Setup time in timing simulation to clock fractions

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Setup time

Is it wrong for the setup time in timing simulation to be larger than T/2, where T is the clock period??
Why or why not??

Thanks in advance..
 

Re: Setup time

Setup time can not be greater than T/2 provided.

If setup time is greater than T/2, Tcq (clock to q) + Tp (Propagation delay) - Tsk (Clock Skew) is less than T/2, which results in setup time violation.

I am not very familiar with timing simulation, don't know how setup time violation affects the simulation.
 

Setup time

Even if the setup time is greater than T/2 whats wrong it satisfies the equation
Tcq+Tp+Tsu-Tsk<T
correct me if I'm wrong
 

Re: Setup time

Thats calculation is correct for achievable clock frequency but, there shouldn't be setup time violation in a circuit.

If you have take setup time is >T/2, Tcq+Tp - Tsk should be less than T at maximum operating frequency, which violates setup time requirement.

If we consider hypothetical case of Tcq + Tp - Tsk is still greater than Tsu, total period is going to be > T.
 

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