setup time/hold time vilation equations

[snappishsen]

Derive setup time/hold time vilation equations for the follwoing circuit? Assume Tcq1 Clock to Q delay,
Tsu1 -- Setup time and Th1 hold time for first FF and similarly Tcq2,Tsu2,Th2 for second FF.

Please find attached the circuit diagram.....

 

[dftrtl]

T_setup_ff1
Tsetup_ff2 <= T_clk + dly2 - max_Input_delay
T_hold_ff1
Thold_ff2 <= min_Input_delay - dly2


T_setup_ff2
Tsetup_ff2 <= T_clk + dly3 - dly2 -Tclk2q_ff1 - dly1
T_hold_ff2
Thold_ff2 <= dly2 + Tclk2q_ff1 + dly1 - dly3

 

[birdy123]

can you please follow up with the following link...

http://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3b.html
and
http://www.vlsi-expert.com/2011/05/example-of-setup-and-hold-time-static.html