Setup time basic understanding

[spaz097]

Hello All,

I am very grateful to this forum for answering a lot of my questions.

However, there is one small concept that i am not quite getting the hang of it.

The question that has been bothering me is the dependency of the transition times of clock signal and data signal on the setup time and hold time of a flip flop.

Please provide any literature or articles , that would help me further understand the implications .

 

[ads-ee]

It stems from the logic threshold levels for high and low logic values. If you have a slowly transitioning signal it takes it longer for that signal to reach a high or low threshold value and be detected as a high or low going transition.

 

[rahul.achates]

Transition time of clock is related to clock skew, when any path is getting analyzed, this transition time will also a part of calculation.

For dats transition time , its clock to q delay , means how much time a signal takes from 1 to 0 or 0 to 1 , that will also be taken in account while calculating the path delay.

 

[birdy123]

Hi,

I hope below 3 articles can help you.

Fix Hold and Setup time 1
**broken link removed**

Fix Hold and Setup time 3

Let me know if you need any other details.