I have a question on setup and hold times. How do foundries arrive at the correct values for setup and hold values while characterizing the cell. Information on the procedure and tools that are used for this will be helpful.
FabHouse gives spice and layout files ,after drawing and extracting netlist from Layout (Eg D FlipFlop) by STARRCXT a net list is obtained.characterisation is done on the netlist with PERL scripting and H-SPice simulations it runs through BISECTION Algorithm i.e,for set up Data should be before Clk and for HOLD data should nt change after clk changes transition.it is performed for many iterations
Actually there is much more into Setup and hold. These timings are calculated with some worst case parameters i.e. the setup time that is shown in the cell is actually is at the worst process corner for setup time (may be SS, FF, TT). The hold time quoted is for the worst process corner for the hold time. Also the foundary test there cells quite well before providing them for any design. So the setup and hold time someone get is actually with some pessimism to accomodate the worst case corner for both setup and hold. Worst case corner of Setup and Hold need not be same. In fact they must be different.
hello everyone, i have a doubt regarding how the setup time gets affected.suppose u delay the clock by Tclk seconds then if the setup time of the d flip flop under for an undelayed clock is Tsu ,now how is my setup time going to change when the clock is delayed.i know the answer but iam unable to convince myself of the same.
the set up time after the clock is delayed will be given by Tsu - Tclk. this can be easily analysed earlier setup time was Tsu now since the clock is delayed by Tclk the input needs to be stable at time Tsu - Tclk. this has an application when the set up time of a circuit is not met the clock can be delayed by using buffers and Tsu can be met but it will be at the cost of decrease in hold time