setup delay in Xilinx ISE post P&R Simulation model

[KHDAK]

Hi All,



I am using modelSim to simulate post P&R simulation model of a processor design generated by Xilinx ISE 13.2 (ABC_timesim.vhd). It appears that there is a setup delay of 100ns in the model and the FF defined in it only start working after that time. Is this delay really part of simulation model and is it possible to change its value?

Regards,

**broken link removed**

Danish

 

[barry]

1) Your attachment is messed up
2) What is your bitmap supposed to be showing us, that something happens at 100nS? We need a little more context.

 

[KHDAK]

1) Your attachment is messed up
2) What is your bitmap supposed to be showing us, that something happens at 100nS? We need a little more context.

Hi,

Yes, the waveform shows the output of a FF from timing simulation file. My simulation works fine when I set initial reset delay of 100ns or more, In my
behavioral simulation the delay was set to 10ns, but now in post P&R timing simulation my design don't work correctly with this value.

 

[barry]

I STILL don't know what your waveform is showing us; those labels on the diagram are meaningless.

 

[KHDAK]

I have re-labeled the waveform. A guy from Xilinx forum says it is an internal reset delay which is exerted upon configuration.


https://obrazki.elektroda.pl/8398369200_1371032469.jpg

 

[barry]

WHAT is "an internal reset delay"? Your waveform does not show the performance of a normal, healthy flip-flop. There is apparently something else going on that is not shown in your diagram. Is there some other signal connected to your flip flop that you are not showing?

 

[KHDAK]

Hi,

No there is no other signal connected to that FF. It works fine If I pulled global reset active for 100ns in my testbench at the start of simulation.

 

[mrflibble]

Are you sure you are using the correct polarity for your reset signal? You have labeled your reset as "active low", but AFAIK xilinx parts use active high by default for the internal reset signals...