setup and hold time of lockup latch

[deepen talati]

We are placing lockup latch in between 2 FFs which are placed in 2 diff. clock domains. And we are making our latch to operate on negative edge of source clock cell. At that time setup and hold time of latch will also come into picture na? So it won't cause any error?? Please clear the doubt

 

[chiranjeevinaidu]

HI deepen,

Basically lockup latches are used scan based design.
1.two different clock domains



> Positive or negative level latch?? It depends on the path you are inserting a lockup latch. Since, lockup latches are inserted for hold timing; these are not needed where the path starts at a positive edge-triggered flop and ends at a negative edge-triggered flop. It is to be noted that you will never find scan paths originating at positive edge-triggered flop and ending at negative edge-triggered flop due to DFT specific reasons. Similarly, these are not needed where path starts at a negative edge-triggered flop and ends at a positive edge-triggered flop. For rest two kinds of flop-to-flop paths, lockup latches are required. The polarity of the lockup latch needs to be such that it remains open during the inactive phase of the clock. Hence,
-> For flops triggering on positive edge of the clock, you need to have latch transparent when clock is low (negative level-sensitive lockup latch)
-> For flops triggering on negative edge of the clock, you need to have latch transparent when clock is high (positive level-sensitive lockup latch)


> connecting the lockup latch to launch flop's clock to reduce the skew between domain1 and lockup latch.so hold timing checking easily met as both skew and uncommon clock path is low. The hold check between lockup latch and domain2 flop is already relaxed as it is half cycle check. So, we can say that the correct way to insert a lockup latch is to insert it closer to launching flop and connect the launch domain clock to its clock pin.

Regards
chiranjeevi

 

[deepen talati]

thank you chiranjivi

I want to show you something. Observe attached 2 fig. which shows the table for 2 cases.
In 1st case where Launch FF is LE(Rising edge enable) and Capture FF is TE(Falling edge enable)
That time it require 2 latches TE following LE

And in the 2nd case Launch FF is TE and capture FF is LE
that time it require no latches.

Why? I am not geting it.
And there will be no combinational logic at all between launch FF and capture FF as they are part of 2 different chains/domains. We are just concatinating those.

Tell me about existance of combinational logic between 2 FFs in above case when we stitching chains...

Waiting for your reply chirajivi

 

[chiranjeevinaidu]

Hi deepen,

mainly lockup latches are used

1..lockup latches necessary to avoid skew problem during shift case of scan based testing
case1 :if launch flop and capture flop sitting for away.( physical design view )
..> it necessary to met skew two different clock domains

case2: both launch and capture flops are placed close each other (physical view)
..> it is not necessary to place lockup latch between two flops

deepen ,this is my understanding based upon my experience,
i have face issue during PN&R physical design

 

[deepen talati]

thank you chiranjeevi..

Chiranjeevi solve my major doubt please.
(1)When there are 2 FFs operated by 2 diff. clocks
FF-1 has clock from 0 to 10 ns
FF-2 has clock from 5 to 15 ns
In that case why we are capturing data at 15 ns and not at 5 ns?
Because there is no comb. delay between them
(2)same case but , there is now latch(lockup) instead of 2nd FF
latch works on low-level means same from 5ns
In that case why data is latching instantly at 5 ns and not at 15ns?
Latch has also its own setup and hold time

waiting for your reply Chiranjeevi