Setup and hold time for output data

[sree205]

Do we consider the setup and hold time with respect to the output data ?

like, the output data has to be there for so much amount of time before it can change ?

i read a paper and this is what i saw.

Tsu(in) = 2.0
Th(in) = 1.0
Tsu(out) = 2.2
Th(out) = 0.8

When do we consider such scenario ? any suggestions ?

 

[semiconductorman]

During synthesis, the set_output_delay command will take care of this. The output delay is the (clock_period - set_up_time_required for the output).

 

[funzero]

tsu(output)2.2 means the output signal will be stable 2.2ns before next clock edge
th(output)0.8 means the output signal will bestabel 0.8 ns after the next clock edge .

 

[zwj_seu]

it/s just timing buget for output pin

 

[yln2k2]

Hi ,

In the above case you should set min out put delay is 0.8 ns as there is a hold req and max is (clk_period - 2.2) .

But just I am thinking about Tsu for In ? any comments ? how it is realted to set_input_delay ?

do you need to set shuch that in InDirection delay max is Tus in ?


regards
yln