You probably want a substantially lower Rout, else as you
approach the dropout voltage you will "wind up" the error
amplifier and have no authority (small signal) over the
output.
The Vgs you can impose, depends on the pass FET gate
drive and pass FET species. A PMOS LDO can impose the
supply difference to the gate (but again you need "room
to move", besides what you'd calculate as a bare ohmic
minimum). A NMOS LDO will have an AUX supply and/or
a charge pump and these are design degrees-of-freedom
to some extent.
If this LDo happens to have a functional schematic in the
datasheet it may offer you these sorts of clues. If not the
presence or absence of an AUX supply may tell you things,
but I have also seen LDOs which "keep it all in house" with
charge pumps inside that you don't see pinned out.