setting input and output delays during synthesis

[S.Nikhil]

Hi,

can anyone tell me about setting input and output delays while synthesizing a design.
What are the factors to consider while setting input delay and outdelays.
Is there any formula to calculate the input delay and output delay based on the clock period of a design.

thx

Nikhil.S

 

[WzWzWz]

1. If the input/output is interface to other chip, refer to the interface electrical spec.
2. If the input/output pin is for other modules in the same chip. depend on the whole chip timing assignment.