csotiriou
Newbie level 2
Hello there, I would appreciate any help on the following issue.
I have a multi-level clock gated design, which I would like to post-synthesis simulate, prior to back-end.
The clock latencies from the root pin to the FFs through the different clock gating cells differ from 10% of T, to 40% of T (inspected by gate-level simulation), more than what I have assigned in Synopsys DC, using the set_clock_latency command, and this I believe is causing HOLD violations.
My question is. What is the quickest and most effective way of appropriately setting the clock latencies through clock gates during synthesis? Do you synthesise first, measure latencies, and resynthesise?
Thanks.
I have a multi-level clock gated design, which I would like to post-synthesis simulate, prior to back-end.
The clock latencies from the root pin to the FFs through the different clock gating cells differ from 10% of T, to 40% of T (inspected by gate-level simulation), more than what I have assigned in Synopsys DC, using the set_clock_latency command, and this I believe is causing HOLD violations.
My question is. What is the quickest and most effective way of appropriately setting the clock latencies through clock gates during synthesis? Do you synthesise first, measure latencies, and resynthesise?
Thanks.