Setting Circuit Initial Conditions in PSPICE

[MahmoudHassan]

Hi
i used two method to set the initial conditions for the node V(1) for the following circuit

the first one i used this statement to insert initial condition on the capacitor
C1 1 0 1uF IC=+1V
and then used flag UIC
.TRAN 500us 10ms 0ms 500us UIC
full statement file :

Investigating Initial Conditions Established by SPICE
VCC 3 0 DC 5V
C1 1 0 1uF IC=+1V
C2 2 0 1uF
R1 1 2 1Kohm
R3 2 4 1Kohm
R2 3 2 1Kohm
R4 4 0 1Kohm

.TRAN 500us 10ms 0ms 500us UIC

.PLOT TRAN V(1) V(2) V(4)
.PROBE
.END

The second one
i used only this statement to set initial condition
.IC V(1) = +1V

Investigating Initial Conditions Established by SPICE
VCC 3 0 DC 5V
C1 1 0 1uF
C2 2 0 1uF
R1 1 2 1Kohm
R3 2 4 1Kohm
R2 3 2 1Kohm
R4 4 0 1Kohm

.TRAN 500us 10ms 0ms 500us 
.IC V(1) = +1V
.PLOT TRAN V(1) V(2) V(4)
.PROBE
.END

There is something wrong i don't understand the outputs from both netlists weren't the same !!!


for the first one The voltage of node 2 V(2) starts from zero as supposed



for The second statements the output was different !
and the voltage at node 2 didn't begin from Zero as supposed but 2.4 V
and V(1) starts from Zero (Which had initial value of 1V)





so i hope you can help me

Thanks a lot for your time

 

[atripathi]

Don't use UIC. This is an old flag and not recommended. If you remove UIC you would get same results in both the cases. And you are correct electrically both are same circuit so results should match. By putting UIC in one case and not putting in another case you are asking simulator to treat these two cases differently and hence the difference in result. If you add UIC in both the case then also you would get the same result. So difference is not due to how you put IC, but due to use of other simulator option.

 

[MahmoudHassan]

Sir thanks a lot for your reply
but which answer is the right the one using UIC or without using it because now i have two simulation results !
which simulation is the correct one ??

Thanks a lot

 

[albbg]

In the first case the you have, at t=0 V(C1)=1 and V(C2)=0 so V1(0)=1, V2(0)=0 and V4(0)=0 this last because V2(0)=0.

In the second case only V(C1)=1 is set while V(C2) is left free, then the initial voltage V2(0) is coming from the calculation of the voltage divider supplied by the 5V and the 1V coming from V1(0).

.IC V(x)=y only set the volatge y at node x all the others are free

UIC uses the initial conditions for all the nodes (as far as I remember the default, if not specified is 0V for cacitors and 0A for inductors)

 

[FvM]

The problem with the original question is that you don't actually tell which initial conditions you consider as right or wrong for the other cicruit nodes. We don't know which problem is simulated by the circuit, so we can't help you with the decisison.

A better explanation of the UIC flag is that it skips the initial transient solution, which is performed ignoring all circuit time constants. Instead all node voltages and branch currents are set to zero, except for those which are directly controlled by an independent source or an IC statement.

In my view, both discussed cases have arbitrary initial conditions, which may or may not represent a real operation state of the circuit.

 

[albbg]

I fully agree with FvM point of view.

 

[MahmoudHassan]

FvM
Thanks a lot for your reply
actually i am studying PSPICE using Adel Sedra Book
and my outputs wasn't the same as the book (using orcad pspice 16.3 ) for the second case
and that was the problem