set_propagated_clock issue

[elamparithi]

Hi Please help me,
While I tried CTS with the ideal clock, the negative slacks are minimal range i.e -30ps.
When i tried to use below command
'set_propagated_clock [all_clocks]' for a single clock module right after the CTS stage(i.e cksynthesis), the higher negative slacks were seen in reg2reg & reg2out paths alone. (i.e -1000ps).

This is not beyond my limit. Why this huge increase in negative slacks for particular paths alone?

Am i in right track or please provide your suggestion?

 

[rahul.achates]

set_propagated_clock will calculate the actual clock delay , I cant say much here. You will have to do analysis why slack is coming negative.

one thing may be, you will have to reduce uncertainty as you are putting actual delay. Output delay also can be reduce. depend on clock frequency and constraint.

 

[elamparithi]

Yes.. thanks for response for my question.

I did the timing analysis on reg2out paths alone at routing stage. For that paths alone, the other end arrival time is not added in timing analysis. But, its added in reg2reg paths.

I will reduce the output delay constriants as per your suggestion.
If i unable to reduce it, can You suggest other type of techniques ?

Is there any commands are available to use along with 'set_propagated_clock' command?
If any, Please notify me.

Thanks

 

[rahul.achates]

There should not be any issue closing timing on reg2out path except if output is not registered.
I think its better to register the outputs , it will increase the DFT coverage also.
Other thing could be , look for the detail path and analysis if tool has added so many buffers at output , it depends on output loading also.

 

[elamparithi]

Yes. thanks for kind reply.

I did following things in my design,
i. Reduced the output delay values based on top level timing.
ii. Did IO arrangements to place logics nearer
But still, i have negative slacks nearly -1.00ns .

My observations:
* When the 'propagated_clock' is introduced, some of delay value is added in 'other End Arrival Time' in in2reg & reg2reg path groups
* But , i unable to see this value in reg2out path groups alone but clock to clock latency delay is included in timing analysis
* How can I add the value in the option of 'other End Arrival Time' ?
* Can I modify the 'set_out_put_delay' command ? or need i change the command 'setAnalysisMode' ?
* Currently i am using below command format
"set_output_delay <delay_value> <output_port_names>" -> used in SDC constraints

"setAnalisMode -checkType setup " -> used in scripts

Need I change above two commands according to propagated clock?

Please correct me. I need to avoid clock latency is added in reg2out path. I understood why the 'other end arrival time' is not added for this path group. Because of, end point is output port which does not have CLK pin.

 

[rahul.achates]

"Please correct me. I need to avoid clock latency is added in reg2out path. I understood why the 'other end arrival time' is not added for this path group. Because of, end point is output port which does not have CLK pin."

U can declare virtual clock and timing output port on that clock.

what is the lunch clock and capture clock ?
Are both clocks coming from same source ?
Is violated path real path ?

post your report here ... then only I will be able to put comments.

rahul

 

[elamparithi]

Yah. Sure .sir. I have explained the issue clearly with reports . please find the attachments

 

[elamparithi]

Yes. Rahul. The violated path is a real path only. Launch and capture clock are same. I have explained all the information in reports shared in previous comment.

I tried below thing also.
* Created virtual clock and constrained the delay for IOs using virtual clock
* used the command 'update_io_latency' command after cksynthesis and before usage of 'set_propagated_clock' command.
* This command adds some network latency value in Input delay and subtracts same value in output delay.
* So that, I am currently seeing slacks in in2reg path only and the 'reg2out' issue is gone.
* Can I use virtual clock constraint delay for Output ports alone? Or need to use the same for input ports also ?