my set up of D-latch is coming independent of capacitive load,is this possible?
if it is not, then can u please tell me where am i doing wrong?
i extracted my D-latch netlist from virtuoso layout editor and working on H-spice.
depends on where the capacitive load you are referring to is. if it's output load, you can add buffers to isolate the latch from the output load and it makes setup time independent from the output load. is that what you're asking for ?
I dont do HSpice model check for standard cells. But the set up time in standard cell libraries is independent from load. Latency is related to laod and trasition time though.
are u sure that setup time is independent of output load, can u give me good reasons for that, anything else concerning this topic is also needed,please help me .
---------- Post added at 10:29 ---------- Previous post was at 10:28 ----------
yes,it is output load but i m not using any buffer.nw can u give me good reasons for that.
The setup time could be dependent or independent of output load. It depends on how you design the latch. However, if the latch is designed in a way that setup time depends on the output load, I'd say that's a poor design.
It would be nice if you send your circuit. In theory setup/hold should not depend on output load because it's mainly defined by switch (if you use switches).