We will now overview the timing requirements for edge-triggered sequential
circuits, which consist of combinational blocks that lie between D flip-flops.
The basic parameters associated with a flip-flop can be summarized as follows:
The data input of the register, commonly referred to as the D input, must
receive incoming data at a time that is at least units before the onset
of the latching edge of the clock. The data will then be available at the
output node, Q, after the latching edge. The quantity, is referred to
as the setup time of the flip-flop.
The input, D, must be kept stable for a time of units, where is
called the hold time, so that the data is allowed to be stored correctly in the
flip-flop.
Each latch has a delay between the time the data and clock are both available
at the input, and the time when it is latched; this is referred to as the clockto-
Q delay,
In the edge-triggered scenario, let us consider two FF’s, and connected
only by purely combinational paths. Over all such paths let the largest
delay from FF to FF be and the smallest delay be Therefore,
for any path with delay it must be true that
136 TIMING
We will denote the setup time, hold time, and the maximum and minimum
clock-to-Q delay of any arbitrary FF as and and respectively.
For a negative edge-triggered register, the setup and hold time requirements
are illustrated in Figure 7.3. The clock is a periodic waveform that repeats
after every P units of time, called the clock period or the cycle time.
The data is available at the launching FF, after the clock-to-q delay, and
will arrive at the latching FF, at a time no later than For correct
clocking, the data is required arrive one setup time before the latching edge of
the clock at FF as shown in Figure 7.3, i.e, at a time no later than
This leads to the following constraint:
For obvious reasons, this constraint is often referred to as the setup time constraint.
Since this requirement places an upper bound on the delay of a
combinational path, it is also called the long path constraint. A third name
attributable to this is the zero clocking constraint, because the data will not
arrive in time to be latched at the next clock period if the combinational delay
does not satisfy this constraint.
The data must be stable for an interval that is at least as long as the hold
time after the clock edge, if it is to be correctly captured by the FF. Hence,
it is essential to ensure that the new data does not arrive at FF before time
Since the earliest time that the incoming data can arrive is
this gives us the following hold time constraint:
Since this constraint puts a lower bound on the combinational delay on a path,
it is referred to as a short path constraint. If this constraint is violated, then
the data in the current clock cycle is corrupted by the data from the next.
clock cycle; as a result, data is latched twice instead of once in a clock cycle,
and hence it is also called the double clocking constraint. Notice that if the
minimum clock-to-Q delay of FF is greater than the hold time of FF i.e.,
(this condition is not always true in practice), then the right hand
side of the constraint is negative. In this case, since the short path
constraint is always satisfied.