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Set and reset pins for a flop is one

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Mar 31, 2012
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Hi folks,

For a flop both set and reset pins are one then the flop goes to unknow state how to over come this situations in industry.

What I know is we can add a delay for any of the pin (set or reset). But on what bases (or) How much delay can I add.

Please let me know as soon as possible.

Thanks in advance,

if your reset and set are asychronous then does it matter? 1st, why would you pass a reset and a set signal so close to other? and 2nd if you did yes youd get an unknown(plus a bit of current draw) but after 1 is released itd go into which ever is still being applied (just like any other transition point is considered an easy way to eliminate this if you feel you have commands that could send both at same time, is to make 1 more dominant then the other, say the reset pin is the output of your reset signal anded with the setb signal. and if you wished to remove possible small glitches during transitions, synchronize it with a clock.


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The adding delay is only usable if yout know when signals are coming, such as a race condition where both are applied near eachother( you can delay 1 to prevent conflict). BUT if you do not know when they are being applied and you add a delay to reset, you could easily get the same situation if there is a reset signal applied followed by a set signal( the reset would be delayed and therefore applied at the same time as the set)

HI Prestonee,

Thank you for your response, Actually this is case a i got in my design In physical design STA how the designer designed I don't know but what I am expecting is not getting, How to overcome this situation.
Actual situation is at 3ns clock is rising edge at the same edge set and reset signals are high. design is getting unknown. value.
adding delay is correct in order to met setup and hold. But what i am not getting is how much delay I am going add.

Thanks in advance

i first ask to verify both are active high. also make sure designer did not accidentally connect one believing it is active low, this could easily be fixed by inverting the control signal along its chain. if they are asynchronous then the delay required would be the amount of overlap that is occurring + margin. may require sim with parasitics to get idea. how long is it in this unknown, and when it leaves is it going back to outputting a delayed d input, or a set or reset?

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