Serial to Parallel Converter VHDL codes

[Sweta25]

Hello Everyone,
I am working on some codes for the serial-to-parallel converter...in fact I need to convert 6 serial values ( from 6 sensors which have already been converted to digital form) to parallel form which will be later fed to a comparator... I wrote some codes but I am encountering some errors...I would highly appreciate some help...

---

Code VHDL - [expand]
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PFA :serial-to-parallel converter 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
 
 
entity SIPO is
    generic (N: integer := 6);
     port(
         clk : in STD_LOGIC;
         Din : in STD_LOGIC_VECTOR(N-1 downto 0);
         Q : out STD_LOGIC_VECTOR(7 downto 0)
         );
end SIPO;
 
 
 
architecture SIPO of SIPO is   
  
component Dff is
    port
    (
    clk : in STD_LOGIC;
    Din(i) : in STD_LOGIC_VECTOR ( N-1 downto 0);
    Q : out STD_LOGIC
    );
end component;
signal s: std_logic_vector (7 downto 0);
 
 
begin
     SIPO : for i IN N-1 to 0 generate
    u0: Dff 
    port map (
    clk => clk,
    Din(i) => Din(i),
    Q => s(0)
    );       
    
    u1: Dff 
    port map (
    clk => clk,
    Din(i) => s(0),
    Q => s(1)
    );
    
    u2: Dff 
    port map (
    clk => clk,
    Din(i) => s(1),
    Q => s(2)
    );
    
    u3: Dff 
    port map (
    clk => clk,
    Din(i) => s(2),
    Q => s(3)
    );
    
    u4: Dff 
    port map (
    clk => clk,
    Din(N) => s(3),
    Q => s(4)
    );
    
    u5: Dff 
    port map (
    clk => clk,
    Din(i) => s(4),
    Q => s(5)
    );
    
    u6: Dff 
    port map (
    clk => clk,
    Din(i) => s(5),
    Q => s(6)
    );
    
    u7: Dff 
    port map (
    clk => clk,
    Din(i) => s(6),
    Q => s(7)
    );
 
    end generate SIPO;
    Q <= s;
 
end SIPO;
 
 
 
 
 
also D flip flop codes
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
 
entity Dff is
     port(
         clk : in STD_LOGIC;
         Din : in STD_LOGIC;
         Q : out STD_LOGIC;
         notQ : out STD_LOGIC
         );
end Dff;
 
 
architecture Dff of Dff is
begin
    process  (clk ,Din)
    begin
        if (rising_edge (clk)) then
            Q <= Din;
            notQ <= not (Din);
        end if ;
    end process;
         
end Dff;

---

here are the errors encountered while simulating sipo codes:
# Error: COMP96_0015: SIPO.vhd : (25, 5): ':' expected.
# Error: COMP96_0018: SIPO.vhd : (25, 5): Identifier expected.
# Error: COMP96_0018: SIPO.vhd : (28, 14): Identifier expected

 

[FvM]

The error is in line 25, as reported in the error message.

Just delete the (i).

 

[ads-ee]

The error is in line 25, as reported in the error message.

Just delete the (i).

More than that...
Everywhere you have something like this:

Din(i) => s(2),
//...
Din(N) => s(3),

should be written like this:

Din => s(2),
//...
Din => s(3),

'(?)' are not allowed as part of a port name.

Besides that your generate statement makes no sense what so ever. It looks like you are trying to improperly implement a shift register, with both instantiating all the DFFs and simultaneously use a generate to do it at the same time. You can only do one or the other...use a generate or instantiate all the DFFs individually.

 

[Sweta25]

Hello,
I rewrote the codes for the Serial to Parallel and problem is that I need 7 8-bit parallel outputs but on stimulating I am getting only 1 8-bit parallel output..the other 6 output are similar....according to my simulation my Din (serial input) is 20 bits.. atleast 2 proper 8-bit parallel output should have obtained...but its not the case..any help would be greatly appreciated...Thanks
my codes

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;


entity SIPO is
	generic (N: integer := 7);
	 port(
		 clk : in STD_LOGIC;
		 Din : in STD_LOGIC;
		 Q   :out STD_LOGIC_VECTOR(7 downto 0); 
		 P1 : out STD_LOGIC_VECTOR(7 downto 0);
		 P2 : out STD_LOGIC_VECTOR(7 downto 0);
		 P3 : out STD_LOGIC_VECTOR(7 downto 0);
		 P4 : out STD_LOGIC_VECTOR(7 downto 0);
		 P5 : out STD_LOGIC_VECTOR(7 downto 0);
		 P6 : out STD_LOGIC_VECTOR(7 downto 0);
		 P7 : out STD_LOGIC_VECTOR(7 downto 0)
		 
	     );
end SIPO;



architecture SIPO of SIPO is   
  
component Dff is
	port
	(
	clk : in STD_LOGIC;
	Din : in STD_LOGIC;
    Q : out STD_LOGIC
	);
end component;
signal s: std_logic_vector (7 downto 0);
signal i: integer := 1;

constant num_cycles: integer := 56;	


begin
	
M1 :
for i in 1 to num_cycles generate		
	u0: Dff 
	port map (
	clk => clk,
	Din => Din,
	Q => s(0)
	);		 
	
	u1: Dff 
	port map (
	clk => clk,
	Din => s(0),
	Q => s(1)
	);
	
	u2: Dff 
	port map (
	clk => clk,
	Din => s(1),
	Q => s(2)
	);
	
	u3: Dff 
	port map (
	clk => clk,
	Din => s(2),
	Q => s(3)
	);
	
	u4: Dff 
	port map (
	clk => clk,
	Din => s(3),
	Q => s(4)
	);
	
	u5: Dff 
	port map (
	clk => clk,
	Din => s(4),
	Q => s(5)
	);
	
	u6: Dff 
	port map (
	clk => clk,
	Din => s(5),
	Q => s(6)
	);
	
	u7: Dff 
	port map (
	clk => clk,
	Din => s(6),
	Q => s(7)
	);	



end generate M1;

L1: for i in 1 to 8 generate
	P1 <= s;	
end generate L1; 
L2: for i in 9 to 16 generate
	P2 <= s;	
end generate L2;
L3: for i in 17 to 24 generate
	P3 <= s;	
end generate L3; 
L4: for i in 25 to 32 generate
	P4 <= s;	
end generate L4; 
L5: for i in 33 to 40 generate
	P5 <= s;	
end generate L5;
L6: for i in 41 to 48 generate
	P6 <= s;	
end generate L6; 
L7: for i in 49 to 56 generate
	P7 <= s;	
end generate L7;
	 
end SIPO;

I am also attaching my simulation
https://obrazki.elektroda.pl/index.php

 

[ads-ee]

You are writing your code like a software program. VHDL is a hardware description language. For loops are not use to iterate over a block of code like you are doing. For loops are used to generate repeated copies of something e.g. multiple instances of a component.

 

[Sweta25]

so what can i use ??? is there any other option???
Problem is that I learnt C programming first then now I am learning VHDL so I tend to use C as a reference...

 

[ads-ee]

Forget everything you know about C when writing HDL. Think of how the circuit needs to be hooked up. If you want a shift register you think of the equivalent schematic design. You were trying to use the for loop to create a "timeline" for how long you shift. That can't be represented in hardware as a loop. To measure time you need to have a counter and look at the value of the counter to determine when you're done.

I'm not even sure you understand the problem statement you were given as an assignment. Do you want seven 8-bit serial-to-parallel converters? Is it okay for the parallel output to change while shifting or should it keep the last valid parallel output until you shift in the next parallel output? Right now you have only a single Din that connects to only a single SIPO shift register. Later code connects the S output bus to all of the parallel outputs. Basically there is only a single instance of the shift register hooked up to all the outputs.

Create a single instance of a SIPO register then instantiate that 7 times using a for loop (if you have to use a for loop per the assignment's requirements).


IMO they should go back and teach schematic based circuit design in school, then teach HDLs by direct translation of schematics to HDL.

 

[Sweta25]

Hi
I need to test my SIPO codes on the Nexys3 board..Actually I am using an Arduino as adc which has as an input from power supply and its output is fed to Nexys3.. The codes then convert this digital serial value to parallel value..On stimulating the codes the desired waveform are obtained but when tested nothing lights up...
Codes for SIPO:

library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;


entity serial is
	 port(
		 S1 : in STD_LOGIC_VECTOR( 0 downto 0);
		 clk : in STD_LOGIC;
		 x : in STD_LOGIC_VECTOR(0 downto 0);
		 P1 : out STD_LOGIC_VECTOR(7 downto 0)
	     );
end serial;


architecture serial of serial is 
component Dff is
	port
	(
	clk : in STD_LOGIC;
	Din : in STD_LOGIC;
    Q : out STD_LOGIC
	);
end component;
	

signal s: std_logic_vector (7 downto 0);
signal i: integer :=1; 
signal clk1 : std_logic;
begin
	clk1 <= clk and x(0); 	
	A0: Dff 
	port map (
	clk => clk1,
	Din => S1(0),
	Q => s(0)
	);		 
	
M1 :
for i in 1 to 7 generate
	Ai: Dff 
	port map (
	clk => clk1,
	Din => s(i-1), 
	Q => s(i)
	);
	
	P1 <= s;
	
end generate M1;

	

end serial;

Codes for Debounce

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity debounce is
	 port(
		 input : in STD_LOGIC;
		 cclk : in STD_LOGIC;
		 clr : in STD_LOGIC_VECTOR (0 downto 0);
		 output : out STD_LOGIC
	     );
end debounce;


architecture debounce of debounce is  
signal d1, d2, d3: STD_LOGIC;
begin
	process (cclk, clr(0))
	begin
		if clr(0) = '1' then 
			d1 <= '0';
			d2 <= '0';
			d3 <= '0';
		elsif cclk'event and cclk = '1' then 
			d1 <= input;
			d2 <= d1;
			d3 <= d2;
		end if;
	end process;
	output <= d1 and d2 and not d3;
	

	

end debounce;



codes for DFF and clkdiv

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;

entity Dff is
	 port(
		 clk : in STD_LOGIC;
		 Din : in STD_LOGIC;
		 Q : out STD_LOGIC
		 
	     );
end Dff;


architecture Dff of Dff is
begin
	process  (clk ,Din)
	begin
		if (rising_edge (clk)) then
			Q <= Din;
			
		end if ;
	end process;
		 
end Dff;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;


entity clkdiv is
	port(
	       mclk  : in  STD_LOGIC;
	       clr : in STD_LOGIC_VECTOR(0 downto 0);
           clk : out STD_LOGIC_VECTOR (2 downto 0);
		   clk47: out STD_LOGIC;
           clk381:out STD_LOGIC
	     );
end clkdiv;


architecture clkdiv of clkdiv is  
signal q: STD_LOGIC_VECTOR (23 downto 0); 

begin
	
     
   process (mclk ,clr(0))
   begin 
	   	   if clr(0)= '1' then 
		   q <= X"000000" ;
	   elsif mclk 'event and mclk  = '1' then 
		   q <= q + 1;
	   end if ;
	  	    end process;
		clk(0)<= q(0);	
		clk(1)<= q(1);
		clk(2)<= q(18);
        clk381<= q(17);
		clk47<= q(20);
	   	
end clkdiv;


top level:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;


entity serial_top is
	 port(
	     JB : in STD_LOGIC_VECTOR( 0 downto 0);
	     sw : in STD_LOGIC_VECTOR(1 downto 0);
		 clk : in STD_LOGIC;
		 led : out STD_LOGIC_VECTOR(7 downto 0)
	     );
end serial_top;



architecture serial_top of serial_top is 
component clkdiv
	port(
		mclk : in STD_LOGIC;
		clr : in STD_LOGIC_VECTOR(0 downto 0);
		clk : out STD_LOGIC_VECTOR(2 downto 0);
		clk47 : out STD_LOGIC;
		clk381 : out STD_LOGIC);
	end component;
	for all: clkdiv use entity work.clkdiv(clkdiv);	

 	
	component serial
	port(
		S1 : in STD_LOGIC_VECTOR( 0 downto 0);
		clk : in STD_LOGIC;
		x : in STD_LOGIC_VECTOR(0 downto 0);
		P1 : out STD_LOGIC_VECTOR(7 downto 0));
	end component;
	for all: serial use entity work.serial(serial);
		
	component debounce
	port(
		input : in STD_LOGIC;
		cclk : in STD_LOGIC;
		clr : in STD_LOGIC_VECTOR (0 downto 0);
		output : out STD_LOGIC);
	end component;
	for all: debounce use entity work.debounce(debounce);
	
	
	signal clk381: STD_LOGIC;
	
	signal output: STD_LOGIC;
begin
	 Label1 : serial
	port map(
		S1(0) => output,
		clk => clk381,
		 x(0) => sw(1),
		P1 => led
	); 
	
	Label2 : clkdiv
	port map(
		mclk => clk,
		clr(0) => sw(0),
		clk381 => clk381); 
	
	Label3 : debounce
	port map(
		input => JB(0),
		cclk =>  clk381,
		clr(0) => sw(0),
		output => output
	);

end serial_top;

 

[TrickyDicky]

The code you have posted doesnt show us anything.
Your serial entity instantiates some other entity called "DFF" that you didnt show the code for.

and I dont know what this debounce entity is for. It doesnt actually debounce the values, it appears to only detect the bounces, and you have set the output to detect opposite values on D2/D1 and D3.

 

[ads-ee]

The code you have posted doesnt show us anything.
Your serial entity instantiates some other entity called "DFF" that you didnt show the code for.

and I dont know what this debounce entity is for. It doesnt actually debounce the values, it appears to only detect the bounces, and you have set the output to detect opposite values on D2/D1 and D3.

It's pretty obvious that the DFF is a D type Flip-Flop, now whether or not it's coded correctly is anyone's guess.

The debounce is a misnamed edge detector and synchronizer (well as currently written).

The code also uses the non-standard libraries std_logic_unsigned and std_logic_arith (taught by those schools that use antiquated syntax)...cclk'event and cclk = '1' is being used instead of rising_edge(cclk). The code (targeted for an FPGA) has a gated clock! The OP is generating clocks from a counter (in an FPGA) instead of generating clock enables. This is another good example of combining all the bad coding practices into a single design.

 

[Sweta25]

I understand gated clock is a bad design practice but this was done in order to "freeze" the parallel..I thought that maybe the arduino is not synchronised which arose the encountered problem...if I remove the debounce codes and the gated clock still I get no results....

 

[ads-ee]

I understand gated clock is a bad design practice but this was done in order to "freeze" the parallel..I thought that maybe the arduino is not synchronised which arose the encountered problem...if I remove the debounce codes and the gated clock still I get no results....

Of course you don't get results, because you are using the "I'll just randomly try this and see if it works" debug methodology.

First carefully check the simulation and the TEST VECTORS you are using. Garbage In = Garbage Out (GIGO). If you are absolutely sure you've supplied the correct vectors to your design in the simulation testbench, now you should make sure the design is doing exactly what you want.

In the case of using counter generated clocks I would strongly recommend adding delays to all the counter outputs to emulate the actual hardware and to prevent the simulator from lying to you if there is some delta time race condition (I've seen this happen before, but that was a long time ago when RTL simulation was in it's infancy). But adding the delays will ensure that nothing funny is going on with those "clocks" (a.k.a. counter outputs).

I also strongly advise you rethink how you design stuff this was done in order to "freeze" the parallel, this would never get past a design review with me working at the same company. If you want to freeze the input use a synchronized clock enable.

process (clk)
  if rising_edge(clk) then
    if (enable) then
      parallel <= some_other_stuff;
    end if;
  end if;
end process;