Serial ADC help needed

[wls]

Hello guys . Wanted to design serial 8/10 bit SAR ADC ( something like AD7995 4-Channel, 10-Bit ADC with I2C-Compatible ) . But I am more towards analog , know little about digital ? Anyone got example ( state-machine/verilog for the control etc ) to do something like AD7995 ? May be I will do it without channel ? Single input enough but need example for the control signal ?

Regards.

 

[MikeR]

example from my last project


// Verilog HDL for "ADC_10b_5M", "logic5" "verilog"

module logic5 (clkp, outreg, cmp, colp, rowp, coln, rown, shp, shn, ready);
input clkp;
input cmp;
output shp;
output shn;
output [0:8] outreg;
output ready;
output [0:15] colp;
output [0:15] rowp;
output [0:15] coln;
output [0:15] rown;

reg ready;
reg [0:3] ct,ct1;
reg [0:7] n,p;
reg [0:15] colp,coln,rowp,rown;
wire [0:3] colnh,colph,rownh,rowph;
reg [0:8] datareg,outreg;
reg shp;
wire shn;

assign shn = !shp;

/*initial
begin
ct = 0;
ct1 = 0;
shp = 1;
end
*/

always @(negedge clkp)
begin
if (ct1==11)
begin
ct1<=0;
ct<=0;
end
else
begin
ct1<=ct1+1;
if ((ct1!=1)&&(ct1!=3)&&(ct1!=5))
begin
ct<=ct+1;
end
end

if (ct1==0) // start definition
begin
shp <= !shp;
ready <= 1;
n[0:7] <= 'b11111111;
p[0:7] <= 'b11111111;
outreg[0:7]<=p[0:7];
outreg[8]<=!cmp;
end
else
begin
ready <= 0;
end

// aproximation

if ((ct>0)&&(ct1!=2)&&(ct1!=4)&&(ct1!=6))
begin
p[ct-1]<=!cmp;
n[ct-1]<=cmp;
end

end
///////////////////////////////////////////



// decoding

assign colph = p[0:3];
assign rowph = p[4:7];
assign colnh = n[0:3];
assign rownh = n[4:7];


always @(rowph)
begin
case (rowph)
4'h0 : rowp = 16'h0001;
4'h1 : rowp = 16'h0002;
4'h2 : rowp = 16'h0004;
4'h3 : rowp = 16'h0008;
4'h4 : rowp = 16'h0010;
4'h5 : rowp = 16'h0020;
4'h6 : rowp = 16'h0040;
4'h7 : rowp = 16'h0080;
4'h8 : rowp = 16'h0100;
4'h9 : rowp = 16'h0200;
4'hA : rowp = 16'h0400;
4'hB : rowp = 16'h0800;
4'hC : rowp = 16'h1000;
4'hD : rowp = 16'h2000;
4'hE : rowp = 16'h4000;
4'hF : rowp = 16'h8000;
endcase
end

always @(colnh)
begin
case (colnh)
4'h0 : coln = 16'h0001;
4'h1 : coln = 16'h0002;
4'h2 : coln = 16'h0004;
4'h3 : coln = 16'h0008;
4'h4 : coln = 16'h0010;
4'h5 : coln = 16'h0020;
4'h6 : coln = 16'h0040;
4'h7 : coln = 16'h0080;
4'h8 : coln = 16'h0100;
4'h9 : coln = 16'h0200;
4'hA : coln = 16'h0400;
4'hB : coln = 16'h0800;
4'hC : coln = 16'h1000;
4'hD : coln = 16'h2000;
4'hE : coln = 16'h4000;
4'hF : coln = 16'h8000;
endcase
end

always @(rownh)
begin
case (rownh)
4'h0 : rown = 16'h0001;
4'h1 : rown = 16'h0002;
4'h2 : rown = 16'h0004;
4'h3 : rown = 16'h0008;
4'h4 : rown = 16'h0010;
4'h5 : rown = 16'h0020;
4'h6 : rown = 16'h0040;
4'h7 : rown = 16'h0080;
4'h8 : rown = 16'h0100;
4'h9 : rown = 16'h0200;
4'hA : rown = 16'h0400;
4'hB : rown = 16'h0800;
4'hC : rown = 16'h1000;
4'hD : rown = 16'h2000;
4'hE : rown = 16'h4000;
4'hF : rown = 16'h8000;
endcase
end

always @(colph)
begin
case (colph)
4'h0 : colp = 16'h0001;
4'h1 : colp = 16'h0002;
4'h2 : colp = 16'h0004;
4'h3 : colp = 16'h0008;
4'h4 : colp = 16'h0010;
4'h5 : colp = 16'h0020;
4'h6 : colp = 16'h0040;
4'h7 : colp = 16'h0080;
4'h8 : colp = 16'h0100;
4'h9 : colp = 16'h0200;
4'hA : colp = 16'h0400;
4'hB : colp = 16'h0800;
4'hC : colp = 16'h1000;
4'hD : colp = 16'h2000;
4'hE : colp = 16'h4000;
4'hF : colp = 16'h8000;
endcase
end


endmodule

 

[wls]

Hello MikeR. Thx a lot for the sample code .

Regards.

 

[FvM]

I'm basically wondering how a 8-bit ADC model would use 64 output bits to control an analog quantity?

 

[MikeR]

I'm sorry. When project start, system was need in 10bit, but from little time we stoped on 9 bit quality. This code for differential 9-bit SAR, logic have 2 8b register N,P for drive par of key on res ladder.

 

[wls]

Hello . Is it possible to share ur thesis or more info on the SAR parts ?