sequence in system verilog

[karthikeie]

Sequence in system verilog

Hi there,
I have some trouble in understanding the working of sequence endsequence in system verilog. Please explain me about the sequence part. What is that ## operator meant for? and what if i change the values???

Thanks in advance...


module sequence_test();
reg a,b,c;
reg clk = 0;

sequence abc;
@(posedge clk) a ##1 b ##1 c;
endsequence

always @ (posedge clk)
begin
@ (abc) $display ("@%g ABC all are asserted", $time);
end



initial begin
$monitor("@%g clk %b a %b b %b c %b", $time, clk, a, b, c);
repeat (2) begin
#2 a = 1;
#2 b = 1;
#2 c = 1;
#2 a = 0;
b = 0;
c = 0;
end
#2 $finish;
end

always #1 clk = ~clk;

endmodule

 

[yourcheers]

https://www.asic-world.com/systemverilog/assertions4.html

 

[srish]

Re: Sequence in system verilog

## is a notation used for timing delays............ ##1 means after 1 clock cycle ..............regarding sequences you make sequences and then use them one by one with some conditions in your assertions(via property)......in assertions we are verifying a sequence or series of sequences..........refer www.testbench.in concurrent assertion section

 

[karthikeie]

Re: Sequence in system verilog

Thanks 4 ur help srish...