Sensor interface with fpga

[Bta241460]

How to interface sensor with fpga using serial communication like uart or i2c? And how to store serial data from sensor with 115200 baud rate on 100 Mhz fpga?

 

[FvM]

UART and I2C interface can be implemented in FPGA fabric. Many examples on the internet.

 

[KlausST]

Hi,

a rather general question. This all has been done million times.
You may use libraries / IPs or you may write the code from scratch. (Not that difficult)

I recommend to do forum search and internet search, then come back with more detailed question.

Klaus

 

[Bta241460]

I am using a lidar sensor, found a working uart code on the internet.
I connected the output data (8 bit) which I have received from sensor to led's and they are blinking continuosly.
I have attached the output data format of the sensor.
How do i store the 9 bytes of data from the sensor to get required range(distance)?

 

[FvM]

You'll copy the received data to a register array for further processing.

 

[Bta241460]

After receiving data from sensor,i have assigned that data to d flipflops as shown below
dout is the 8bit data received from sensor using uart
df is the d flipflop module
0 and 1 byte are fixed header 0x59
Wire [7:0] d8;
assign d8=dout;
df d8(.d(d8),.clk(clk),.q(q8));
df d7(.d(q8),.clk(clk),.q(q7));
df d6(.d(q7),.clk(clk),.q(q6));
df d5(.d(q6),.clk(clk),.q(q5));
df d4(.d(q5),.clk(clk),.q(q4));
df d3(.d(q4),.clk(clk),.q(q3));
df d2(.d(q3),.clk(clk),.q(q2));
df d1(.d(q2),.clk(clk),.q(q1));
df d0(.d(q1),.clk(clk),.q(q0));
always@(posedge clk)
begin
if(q0==8'h59 && q1==8'h59)
dstnc=q2+q3*256;
else
dstnc=8'b00001111;
end
I have connected the dstnc output to a 7 segment display and it is showing 15(8'b00001111)
Did i made any mistake in the above code?

 

[FvM]

I presume dout is the UART output register, but what is clk? Is it the UART data ready signal? If so the design could work by chance, but it's no proper synchronous logic. We expect one fast clock driving UART and decoding logic and all events (e.g. UART oversampling clock, bit clock and data ready signal) represented by clock enable signals or flags that last for one clock cycle. Respectively you'll use a DFF with enable rather than a simple DFF for the shift register line.

 

[Bta241460]

Clk is the system clock -100Mhz-----t=10ns
Sensor baud rate is 115200 -
1/(115200)=8.68 *e(-6)
Which means i need 870 clock cycles to get data
Here in the previous post
(assign d8=dout) ,
while assigning dout from uart to d flip flop
Should i wait for 870 clock cycles or i have to assign in the single clock?

 

[FvM]

Suggest to look at an existing UART design. UART RX needs oversampling, usual factor is 16. Instead of generating a dedicated oversampling clock, you can run the clock divider in the uart_rx code, see example below.

See also previous Edaboard threads, e.g.:

https://www.edaboard.com/threads/rs-232-receiver-and-transmitter-design-in-vhdl.137269

fpga4fun.com - Serial interface (RS-232)

 

[Bta241460]

I have tried the code which you suggested, and still not getting the output.
correct me if i made any mistake in the code(attached below)

 

[FvM]

q<=0 surely isn't right, it will permanently reset the DFF, just omit the else statement.

module df(
    input wire [7:0] d,
    input wire enable,
    input wire clk,
    output reg [7:0] q
    );
    always@(posedge clk)
    begin
    if(enable==1)
    q<=d;
    else 
    q<=0;
    end
endmodule

There are probably more errors, you'll usually test the code in a simulation first.