sensitivity to bloking and non-blocking assignments of Verilog

[ASIC_int]

A simulator is sensitive to bloking and non-blocking assignments of Verilog. Does a synthesis tool is sensitive to bloking and non-blocking assignments.

 

[FvM]

Strictly spoken, sensitivity is to events rather than assignments. I guess you mean, an event possibly caused by a value change?

As a next point, sensitivity doesn't exactly exist in synthesized logic. Level sensitive events are basically ignored in synthesis, edge sensitive events translated to clocked registers. That's quite different from simulation, where simulation of blocks is actually schedule based on events.

 

[ASIC_int]

FVM

I am talking of sensitivity of blocking assignements. I mean to say that for blocking assignments the assignments happen sequentially and for nonblocking assignments the assignments happen parallel. A simulator maintains this sensitivity of blocking statements happening sequentially and nonblocking statements happening parallel. But does the synthesis tool ALWAYS take care of sequential nature of blocking assignments while doing synthsis? Is the synthesis tool sensitive enough to take care of the sequential nature of blocking assignments and parallel nature of nonblocking assignments?

I have an IEEE document that provides an example which makes me to infer that the sequential nature of blocking assignments are not taken care for synthesis tool.

Regards

 

[FvM]

I assume, that the sequential nature will be implemented correctly inside an always block, but not beyond it.

You should give an example of a construct, where you expect problems in synthesis.

 

[ASIC_int]

Thanks for your reply. We are looking for confirmation not an assumption.