Hi Boopathy,
Whether the 50MHz clock and the 100MHz are synchronous clock or asynchronous?
If they are asynchronous, then you should follow any of the CDC design, like DMUX/MUX synchronization mechanism or Double flopping mechanism.
If they are synchronous, then you can make a select/control signal from the 100MHz clock, means create a signal say "sig_100_by_2",
then on reset make it low, then toggle the signal in 100MHz clock. So you will get a signal which is in 100MHz domain but its frequency will be 50MHz,
then you can use this "sig_100_by_2" signal through out your 100MHz domain, means once the "sig_100_by_2" is high then you can performs the operations you want
and if the "sig_100_by_2" is low you can do nothing.