Good practice to put something like a .1 uF ceramic in parallel with a 10 or more uF
tantalum.
A good way of evaluating bypass effectiveness is using scope on infinite persistence,
look at target supply rail and see what pk-pk noise looks like. Let scope run for a min
or two in this mode.
Also set scope for "normal" triggering, edge, and set trig level for Vss - .5, then
after a minute or two set it to Vdd + .5. To see if you get any triggers outside supply
rail which can cause unpredictable results in a chips operation, in extreme CMOS
latchup.
Bypass cap effectiveness (technology of cap) :
Regards, Dana.