Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

segment the image using VLSI code

Status
Not open for further replies.

aara

Newbie level 5
Joined
Apr 22, 2013
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,391
i want to segment the two layers (2 circles)in my image. I read the image using pixel values in modelsim. Now i planned to segment the layers by comparing the pixel values. In that code i got two errors..I dnt know how to proceed and how to view output in the modelsim ...please help...

This is my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_1164.std_ulogic ;
use std.textio.all;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity image_read is

--port(Q : out std_logic);
--type img_array_t is array(natural range <>, natural range <>) of natural;
--signal img_array : img_array_t(0 to 59, 0 to 9));

end image_read;

architecture Behavioral of image_read is

type img_array_t is array(natural range <>, natural range <>) of natural;
signal img_array : img_array_t(0 to 165, 0 to 165);
--- signal Q := "100" ;

begin

recievedata: process
file img_file : text open read_mode is "crt.txt";
variable l : line;
variable temp : natural;
--variable t : natural;
begin


for y in 0 to 165 loop

readline(img_file, l);

for x in 0 to 165 loop
read(l,temp);
img_array(x,y) <= temp;
if (temp < '60') then
img_array (x,y) <= Q ;
end if ;
end loop;
end loop;
wait;
end process;

process
file outfile : text is out "out.txt";
variable outline : line;
variable temp : natural;
begin

write(outline, temp, right, 16);

writeline(outfile, outline);


wait;
end process;
end Behavioral;



errors


# ** Error: D:/x code/loop/loop.vhd(64): near "'": syntax error
# ** Error: D:/x code/loop/loop.vhd(70): near "loop": expecting "PROCESS"


please help....
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top