seconds on 7 seg display verilog code

[mzaina]

seconds on 7 seg display

hi all

i need help with this verilog code.

it supose to display the seconds from 1s to 60s on 7 seg displays and reset.

no errors but wrong output

please help .



module seconds (clock,counter,clock_1Hz,enable,counter_s0,Hex_s0,counter_s1,Hex_s1);

input clock;
output reg [23:0] counter;
output reg clock_1Hz;

input enable;
output reg [3:0] counter_s0;
output reg [6:0] Hex_s0;

output reg [3:0] counter_s1;
output reg [6:0] Hex_s1;


always@ (posedge clock)

begin

counter <= counter+1;
if (counter==24'hCDFE60)

begin

clock_1Hz <= !clock_1Hz;
counter <= 0;

if (enable == 0)

begin

counter_s0 <= counter_s0+1;

if (counter_s0== 4'b1001)

counter_s1 <= counter_s1+1;

case (counter_s0)

4'b0000: Hex_s0 = 7'b1000000;
4'b0001: Hex_s0 = 7'b1001111;
4'b0010: Hex_s0 = 7'b0100100;
4'b0011: Hex_s0 = 7'b0110000;
4'b0100: Hex_s0 = 7'b0011001;
4'b0101: Hex_s0 = 7'b0010010;
4'b0110: Hex_s0 = 7'b0000010;
4'b0111: Hex_s0 = 7'b1111000;
4'b1000: Hex_s0 = 7'b0000000;
4'b1001: Hex_s0 = 7'b0010000;
endcase

case (counter_s1)

4'b0000: Hex_s1 = 7'b1000000;
4'b0001: Hex_s1 = 7'b1001111;
4'b0010: Hex_s1 = 7'b0100100;
4'b0011: Hex_s1 = 7'b0110000;
4'b0100: Hex_s1 = 7'b0011001;
4'b0101: Hex_s1 = 7'b0010010;
4'b0110: Hex_s1 = 7'b0000010;

endcase

end

else begin

counter_s0 <= 0;
counter_s1 <= 0;
end

end


end

endmodule

 

[vipinlal]

Re: seconds on 7 seg display

Though I dont know much verilog coding, but you can try the following:

Put an "end" immediately after the following statement in the code:

if (counter_s0== 4'b1001)

counter_s1 <= counter_s1+1;


What I meant is that put the case statements outside the conditional statements.

also tell us what kind of output you are currently getting.

--vipin
https://vhdlguru.blogspot.com/

 

[mzaina]

seconds on 7 seg display

thank you for trying to help me, but still it displays 00 on 7 seg displays before and after your suggestion although the 1Hz clock working properly !!

 

[vipinlal]

seconds on 7 seg display

Just a small doubt.
You have used "clock_1Hz <= !clock_1Hz; " this to generate 1 Hz clock. But you havent used this clock anywhere in your code.
Are you missing a statement like this :
always@ (posedge clock_1Hz) .

And make sure that enable input is always '1'.Otherwise it will display "00" always.

--vipin
https://vhdlguru.blogspot.com/

 

[mzaina]

seconds on 7 seg display

i need this clock to generate 1 Hz clock means time= 1 second from internal clock 27Mhz.

can i write always inside always?

 

[vipinlal]

Re: seconds on 7 seg display

I dont think you can use nested 'always' statement in verilog. That would mean that the signals are driven by two clocks,which is not synthesisable.
You have generated the 1 Hz clock, but havent used an 'always' statement with it.

--vipin
https://vhdlguru.blogspot.com/

 

[mzaina]

seconds on 7 seg display

you are right it was missing

always@ (posedge clock_1Hz)

and i add if ... if else

and it worked ...

Thanks a lot