Binome
Full Member level 3
- Joined
- Nov 16, 2009
- Messages
- 153
- Helped
- 2
- Reputation
- 4
- Reaction score
- 2
- Trophy points
- 1,298
- Location
- Lyon, France
- Activity points
- 2,412
Hi,
I'm using qsys to implement a system on Quartus II.
I use a DE0-NANO board and I want to access the SDRAM. I want to access it from a Nios II (and also from the hardware design but it's another problem) so I've instantiated a SDRAM controller in qsys, it's configured like this: 32-bit wide, 1 chip select, 2 banks, 14 rows, 8 columns. I don't understand it precisely. It tells it's 32 MBytes-wide. There's a s1 port that I connect to the cpu and a "wire" port. I don't understand what it is. I exported it as I'd like to connect it to the sram pins but it tells I have a 14-bit address port, a cas, a ras and a ba so it seems to me I can only write 2^17 bytes and not 32M. Please tell me how it works.
I'm using qsys to implement a system on Quartus II.
I use a DE0-NANO board and I want to access the SDRAM. I want to access it from a Nios II (and also from the hardware design but it's another problem) so I've instantiated a SDRAM controller in qsys, it's configured like this: 32-bit wide, 1 chip select, 2 banks, 14 rows, 8 columns. I don't understand it precisely. It tells it's 32 MBytes-wide. There's a s1 port that I connect to the cpu and a "wire" port. I don't understand what it is. I exported it as I'd like to connect it to the sram pins but it tells I have a 14-bit address port, a cas, a ras and a ba so it seems to me I can only write 2^17 bytes and not 32M. Please tell me how it works.
