SDR-SDRAM memory controller- CAS latency setting?!?!??!?!?

[nu_ema_e]

sdram cas latency

Hi All,


In order make my SDRAM work I need to configure SDRAM CAS latency=2,
while the memory controller is configured for CAS latency=3.
If I set both CL=2, the memory controller samples the data one cycle too early.
This looks like a problem...

I'm using ARM's PL172 MPMC core, but my question is more general:

From your expirience with memory controllers, does the "CAS latency" specification in memory controller manuals referes to the CAS latency that the SDRAM is configured at? Or does it refers to the number of clock cycles that the memory controller has to "wait" before it gets the data from the SDRAM?

The MPMC datasheet is quite ambiguous about this issue.


Thanks,
David.

 

[hem_wall]

sdram memory controller

Hi ,
the cas latency is related to both sdram memory and also controller.
if the cas latency is 2,the read data will come 2 clock cycles later after the read
command is issued.

iworked on ddr and ddr2.i think the cas latency is only related to memory in ddr
and ddr2 case.because the dqs is used to qualify the data.only during initialization
cas latency is to be programmed into the memory according to the memory clock speed.