nu_ema_e
Newbie level 3
sdram cas latency
Hi All,
In order make my SDRAM work I need to configure SDRAM CAS latency=2,
while the memory controller is configured for CAS latency=3.
If I set both CL=2, the memory controller samples the data one cycle too early.
This looks like a problem...
I'm using ARM's PL172 MPMC core, but my question is more general:
From your expirience with memory controllers, does the "CAS latency" specification in memory controller manuals referes to the CAS latency that the SDRAM is configured at? Or does it refers to the number of clock cycles that the memory controller has to "wait" before it gets the data from the SDRAM?
The MPMC datasheet is quite ambiguous about this issue.
Thanks,
David.
Hi All,
In order make my SDRAM work I need to configure SDRAM CAS latency=2,
while the memory controller is configured for CAS latency=3.
If I set both CL=2, the memory controller samples the data one cycle too early.
This looks like a problem...
I'm using ARM's PL172 MPMC core, but my question is more general:
From your expirience with memory controllers, does the "CAS latency" specification in memory controller manuals referes to the CAS latency that the SDRAM is configured at? Or does it refers to the number of clock cycles that the memory controller has to "wait" before it gets the data from the SDRAM?
The MPMC datasheet is quite ambiguous about this issue.
Thanks,
David.