chip-monk
Newbie level 5
When I try to do an sdf annotation in Cadence I get lots of warnings like:
ncelab: *W,SDFGENNF: Generic "TPD_ip1_op_posedge" not found in component "test.dff_1.g16:" <./gen_test1.sdf, line 20>.
The generic "TPD_ip1_op" is present in the library vhdl model file but the _posedge generic is not present.
Upon searching much forums online, most cited the reason being incompatibility of the SDF file generated with VITAL's older version.
I also read that synopsys has options like:
sdfout_no_edge = "true";
What is the equivalent method in Cadence?
Also, my set up is as follows:
The synthesized netlist in in Verilog, whereas the cell definitions are in VHDL.
NC in Cadence provides functionality to compile both Verilog and VHDL together and also for a combined SDF annotation.
The procedure for annotation is to generate the design.sdf.X first using ncsdfc, then specify the sdf options during ncelab command.
ncelab: *W,SDFGENNF: Generic "TPD_ip1_op_posedge" not found in component "test.dff_1.g16:" <./gen_test1.sdf, line 20>.
The generic "TPD_ip1_op" is present in the library vhdl model file but the _posedge generic is not present.
Upon searching much forums online, most cited the reason being incompatibility of the SDF file generated with VITAL's older version.
I also read that synopsys has options like:
sdfout_no_edge = "true";
What is the equivalent method in Cadence?
Also, my set up is as follows:
The synthesized netlist in in Verilog, whereas the cell definitions are in VHDL.
NC in Cadence provides functionality to compile both Verilog and VHDL together and also for a combined SDF annotation.
The procedure for annotation is to generate the design.sdf.X first using ncsdfc, then specify the sdf options during ncelab command.