SDF errors during simulation and switching activity !!!

[Arik]

Hi ,

Can the SDF errors during gate level simulation affect on capturing of switching activity info for power analysis ???

thanks in advance

 

[act3eee]

I think that depends on the tools you are using. Better consult your vendor.

SDF errors => the timing delays are not correct => if the power analysis tools estimate the power based on your dynamic test bench, the analysis is certainly not correct.

 

[funzero]

during simulation , SDF annotation error may cause the simulation tools to stop.
even if the sdf warining may deduce an incorrect switch activities , so i think ,this may cause an variation in your estimation.

 

[Arik]

thanks a lot !!!

and one more question ...

How long should the simulation run in order to capture enough switching activity info for Power Estimation ???

P.S. I'm using Power Compiler for power estimation and VCS for simulation !!!

 

[eda_wiz]

thanks a lot !!!

and one more question ...

How long should the simulation run in order to capture enough switching activity info for Power Estimation ???

P.S. I'm using Power Compiler for power estimation and VCS for simulation !!!

power compiler reports average power. so the simulation time doesnt matter, if ur test vectors represent a realistic data in actual working condtions.

But typically Power estimation accuracy will increase with the simulation time .
rgds