sdf annotation problem

Status
Not open for further replies.
R

richardhuang

Member level 2
Joined
May 26, 2005
Messages
44
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
china
Activity points
1,569
sdf annotation

when i annotate my netlist, this simulation just run about 30ns and stoped, seemly going into loop, but if i did not annotate my design, the simulation can go ahead,i can not find the problem, can you help me or give a suggestion?
 

1st: Make sure that the SDF annotation has finished correctly, you should see a message like: SDF Backannotation Successfully Completed.”

2nd: Did you check (trace) the clocks and resets of your chip? I would start looking at them, they most likely went undefined and maybe this is the reason why your simulation is hanging.

IF CLK and RESET are OK THEN: Do you see any violation messages after reset? They can give you a clue why things are not working. Maybe an asynchronous clock domain crossing is causing the problem. Turn off the notifiers on these domain-crossing f-flops.

good luck!!!

cheers
 

Thank you for your suggestion! the simulation is hanged before reset release. and in this period, only referenced clock exits and any clocks in inner chip do not generate.i guess maybe some moduel should be initialized during reset.
 

Maybe some configuration register is missing a reset. This isn't a real chip problem but it brings pain to the GL simulation. You will have to find out which register it is and do some trick to initialize it:

One way is work with forces: Force the Q of these uninitialized FFlops to $random until the chip reset is released.

Another way is to replace the cell instantiation of these uninitialized FFlops with some hacked library cell which does not generate Xs. Make sure you only replace these very flops which are not being initialized.

hope it helps

cheers
 

I guess you are right, because this issue is related to some X state of flip-flops. because in our design , there have so large mount of syncronous logic. and which will result in x state when do post simulation.i have jump the issue with a new environment and can make sure of the root of the issue is same as you describe.but now i haven't locat the flip-flop. thank you very much
 

keep all setup and hold 0 and than check .
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…