I am performing the last timing checks to my placed and routed design. Using Innovus I wrote the SDF and .v verilog file, which I then used in NCSim. Although everything went as expected, when compiling the testbench (where I issue the sdf_annotate command), I get the following output log:
In the number of TChecks I would be expecting 100% coverage as well. Is this normal? Honestly, I was expecting to hit the 100 % rate as well. Any opinions regarding this?
Well, when simulating the design, if I set a running clock frequency higher than the one I used to synthesize the design (during place and route and etc) I get a lot of warnings indicating setup/hold time violations, so, I would assume that the timing checks are properly in use..
But any more suggestions? Or somehow this time check are related to something else?