SDC: How to set delay in a clock path

[NikosTS]

Hello everyone,
I have a design where on the top level I have a clock signal as a port and I want to make sure it arrives with a delay at a specific pin inside the hierarchy.
I tried something : set_min_delay 0.5 -from CLK -to hier1/CLK (where hier1 is the module and CLK is the module's clock pin ) and I would expect to have some buffers/delay cells inserted.
However it doesn't seem to make a difference.

Any ideas on how to proceed?

Thank you

 

[ThisIsNotSam]

Is it still wrong in this situation to try and delay the clock for lets say 1.2ns in order to capture the correct address value?

model the signal delay correctly. let the clock be. if your sram takes 1.2ns to respond, you cannot have a clock period of 1ns (unless you do unusual tricks like MC paths). your sram is the bottleneck of your design. live with it.