beowulf
Member level 4
Hi all,
This might be the most comon problem/task for ASIC engineers. I need a script that will generate a top level module for 'n' verilog modules (in 'n' files)
Say I have A.v & B.v. The script should generate a ABTop.v such that
module ABTop(
clk
:
:
);
input clk;
input (etc etc)
:
:
output (etc etc)
:
:
A A_i (
.clk (clk)
:
:
:
);
B B_i (
.clk (clk)
:
:
:
);
endmodule
This can be a perl, tcl, shell script...Any pointers will be helpful
Thanks,
B
This might be the most comon problem/task for ASIC engineers. I need a script that will generate a top level module for 'n' verilog modules (in 'n' files)
Say I have A.v & B.v. The script should generate a ABTop.v such that
module ABTop(
clk
:
:
);
input clk;
input (etc etc)
:
:
output (etc etc)
:
:
A A_i (
.clk (clk)
:
:
:
);
B B_i (
.clk (clk)
:
:
:
);
endmodule
This can be a perl, tcl, shell script...Any pointers will be helpful
Thanks,
B