Hi all,
This might be the most comon problem/task for ASIC engineers. I need a script that will generate a top level module for 'n' verilog modules (in 'n' files)
Say I have A.v & B.v. The script should generate a ABTop.v such that
The logic is not an issue, I just wanted to know if somebody has done this already (its a common problem) so the wheel need not be reinvented.
btw, readers of this post can take a look at a tool called Topweaver (just google topweaver) which is a GUI based top level module creator. Pretty neat, but a script based tool will be nicer.
There was a site called tclforeda.com which supposedly had such tools, but the site doesnt exist anymore...