Schematics on Vivado

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Mustaine

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Hello friends
i am currently studying the book digital circuits by morris mano and i am solving a problem which trying to draw the circuit below(Four‐bit binary counter with parallel load) but on vivado i do not know why but the circuit i draw quite different from the book example.
Did i do something wrong?
HDL seems okay. Do i interpret the schematics wrongfully i am not sure cause it looks a mess.
Can you give me some advice .
Thanks in advance.
 

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In the textbooks, a digital logic is typically explained using the basic gates and flops.

When you implement a digital logic with a FPGA, the tool will show you the implementation in terms of look-up tables (LUT), flip-flops and multiplexers. The gates you see in the textbook are implemented using LUTs (the schematic pic). So don't get confused.
 

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