Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Schematic for interwire crstalk&delay measurement![help]

Status
Not open for further replies.
C

cadenceUK

Member level 5
Joined
Aug 15, 2007
Messages
90
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,862
0_1187155531.jpg


Please suggest me !

The circuit gives attenuated value for same bit patteren and devastating output at opposite bit patteren!
 

Oh! I finally resolved the thing and checked that i was missing the power supply!

Now , I am wondering about the place where i should give the supply?

@ top level
OR
@ inverter level
OR
Both?

Thx in anticipation.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top