Schematic and spice netlist do not match

[william_luo]

Maybe this is a silly question. I need to use Nangate OCL to make a design. But when I checked the schematic and spice netlist provided all by 45nm Nangate OCL, I found that the schematic and spice netlist do not seem to match (Drain and Source). The schematic and netlist are shown below (take AND2_X1 as an example),


...........
M_i_2 net_0 A1 ZN_neg VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_3 VSS A2 net_0 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 ZN_neg A1 VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_5 VDD A2 ZN_neg VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_1 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
...........

The terminal should be defined in the order of (Drain, Gate, Source, Body), but it seems not right. Can anybody help explain this?
Thanks in advance.

Wayne.

 

[dick_freebird]

Source and drain are permissible to swap, in standard CMOS.
Only if you have an asymmetric device design (drain-only
extended, or source strapped to body internal to the
PCell) is this not true.

Take up your ideas of "should" with the netlist procedure
call, and any layers of subcircuit or schematic below symbol.

 

[william_luo]

Thanks a lot and it's quite useful for me.

Regards,