scan mode input/output delay constrain

[jjww110]

when in scan mode , how to set appropriate input/output delay for scan in / scan out ports and primary input /output ports,
thx in advance !!

 

[maulin sheth]

You can check in the command also...
for DFT Compiler from Synopsys : command like set_input_delay, set_output_delay , test_default_delay etc...
you can just check that how to use this commands....

 

[jjww110]

i want to know the appropriate value for the input/output delay , not the command itself , thank u!

 

[maulin sheth]

That is totally depends on the technology....its not constant always...

 

[jjww110]

can u tell me some case, such as .18 tech ,thank u!

 

[maulin sheth]

Can you tell me what is the purpose to know this...its around 1ns or 2ns.....

 

[jjww110]

for sta scan mode timing check,thank u ,maulin sheth !

 

[sam536]

Scan mode IO delays doesnt depend on Technology. Its purely based on your Tester . Fabs/product company uses VLCT(Very low cost Tester) or any other tester . Tester will have { 45 55} duty cycle. The test clock will be around 20-50Mhz. The pulse need to check for on and off time and write the IO delay constraints.

Search for VLCT tester related timing in google to get the values.

More over, Input and output delays wont have hardcoded values. Its always % of clock period or depends on the combo logic between port to first register in the design or vice versa.

Thanks. Sam

 

[maulin sheth]

I don't think so that it is depends on the tester..because Scan Mode ports which are already fabricated for particular technology and once ports are inserted that it is the part of the design for specifically fabrication...and all the libraries used for inserting the scan logic is also for specific technology...yea that is true that it is not hard coded value...but this case is same for other logic delay also...

 

[sam536]

because Scan Mode ports which are already fabricated for particular technology and once ports are inserted that it is the part of the design for specifically fabrication...and all the libraries used for inserting the scan logic is also for specific technology......

Which of the Scan mode ports are fabricated for particular technology. ??..

Did you heard about Functional ports also can be used in Scan mode to stich the Scan chains?. SI and SO are not dedicated ports...

If Scan mode ports are Technology dependent, How come RTL is independent of technology?.... ....

Thanks Sam

 

[maulin sheth]

Which of the Scan mode ports are fabricated for particular technology. ??..

Did you heard about Functional ports also can be used in Scan mode to stich the Scan chains?. SI and SO are not dedicated ports...

If Scan mode ports are Technology dependent, How come RTL is independent of technology?.... ....

Thanks Sam

But RTL is synthesized for paticular technology...
and in most of the cases, Scan logic is inserted on the gate level netlist...

 

[sam536]

But RTL is synthesized for paticular technology...
and in most of the cases, Scan logic is inserted on the gate level netlist...

Do you insert Scan mode ports during Scan insertion?. Cant we use the same functional ports for Scan in And Scan out during Scan chain insertion?.

In DFT configuration file, wont you sepcify for each scan chain, what is your SI and wahts your SO pin?.. Then Why tool need to insert a port during the scan stiching in Scan insertion?.

Thanks Sam

 

[maulin sheth]

We can use the functional ports for SI and SO, but this is different topic and this is the case when there is limitation of ports...But in general, Scan mode ports are different from the functional ports.
Yea we just create the new port for Scan mode during Insertion...But for this also we need the specific technology library..
What I thing is that, if the design is of specific technology, thn after fabrication, scan ports are also the part of the design..and its also fabricated in the same manner as the other ports...So its delay depends on the technology...
Can you tell me that, Scan ports are fabricated differently from the other functional ports or not?

 

[sam536]

Do you mean Pads ?. PAD delay is specific to technology . There is no difference between functional pad or Scan port pads. Do you agree? .
Now, When you are considering the IO delays, PAD delays play an important role . You mean Its technology dependepnet.

But, how did u conclude 1 or 2ns for 0.18um tech IO delay?. does it not depend on the Tester supporting clock frequency?.

 

[maulin sheth]

Of course man...
I have not conclude...but I read at somewhere...and jiww110 require just value to check it....During delay STA, we know the functional frequency and also scan frequency...DFT guy need to clear the timing for the Scan path also..which include all delay...
Tester frequency is already decided during scan insertion, This is not dependent on the tester clock...but to decide scan frequency, we need to check the tester support of frequency..but it is decided at very early stage....

 

[sam536]

Which means, Scan mode Input delay is :
---> Scan CLOCK Period (Depends on the Testr Clock Wafeform)- PAD delay -Combo logic from the port to first register in the Scan chain.

For Ex:
Scan clock freq is 50Mhz, The clock is 20ns (if waveform is 50-50%, which is very unlikely), PAD delay is 10ns, and combo (which CLK->Q) and net delay) is 1ns,
Input delay is 20 - 10 -1 => 9ns.

Same way need to calculate for Scan output port...

Regards Sam

 

[maulin sheth]

Yea...its true..

 

[james12345]

SID used in STA process and to meet setup time: SID + data delay + Tsu < Cperiod + Cdelay
However, in scan shift, the data (within the same clock cycle) must reach first register before the rising of same clock cycle.
Do we need to translate the SID based on that as well?

 

[maulin sheth]

Yea. Ofcourse...That's why we have a procedure called test_setup for initialization in the generated patterns itself...

 

[james12345]

Yea. Ofcourse...That's why we have a procedure called test_setup for initialization in the generated patterns itself...

No, what I am saying is: assuming the following waveform @50MHz clock:
Scan input: 0/1 { '0ns' D; }
Scan clock: P { '0ns' D; '5ns' U; '15ns' D; }

Scan data need to reach first register before rising edge of clock @5ns. But from STA process, setup time check is measured against next clock edge. My question is: do we need to model the SID to reflect this situation?

Example: if the internal data delay is 3ns, what will be the value for SID setting?