sampham04
Junior Member level 2
Hi,
I inserted a scan chain into a circuit using Synopsys DC then simulated it through Tetramax, but only got a fault coverage of 6.67%. I'm not exactly sure what the problem is, but I think it might have something to do with the way my scan chain was inserted.
The code I am trying to insert a scan chain into is:
module dff(CK, Q, D);
input CK, D;
output Q;
reg Q;
always@(posedge CK)
Q <= D;
endmodule
module s27(GND,VDD,CK,G0,G1,G17,G2,G3);
input GND,VDD,CK,G0,G1,G2,G3;
output G17;
wire G5,G10,G6,G11,G7,G13,G14,G8,G15,G12,G16,G9;
dff DFF_0(CK,G5,G10);
dff DFF_1(CK,G6,G11);
dff DFF_2(CK,G7,G13);
not NOT_0(G14,G0);
not NOT_1(G17,G11);
and AND2_0(G8,G14,G6);
or OR2_0(G15,G12,G8);
or OR2_1(G16,G3,G8);
nand NAND2_0(G9,G16,G15);
nor NOR2_0(G10,G14,G11);
nor NOR2_1(G11,G5,G9);
nor NOR2_2(G12,G1,G7);
nor NOR2_3(G13,G2,G12);
endmodule
And the steps I used to create the scan insertion are:
set_scan_configuration -style multiplexed_flip_flop
compile -scan
set_dft_signal -view existing_dft -type ScanClock -port CK timing[list 40 60]
create_test_protocol
dft_drc
set_scan_configureation -chain_count 1
preview_dft
insert_dft
write -format verilog -hierarchy -output s27_dft.v
write_test_protocol -out s27_dut.spf
After that I don't get any errors, but I do get this warning:
The multi-clock protocol requires that the strobe time be before a clock's pulse if it is used for transition fault testing. (TESTXG-56)
Do you have any ideas of something I should change or add in order to increase my fault coverage to an acceptable amount?
Any suggestions you have would be much appreciated.
Thank you!
I inserted a scan chain into a circuit using Synopsys DC then simulated it through Tetramax, but only got a fault coverage of 6.67%. I'm not exactly sure what the problem is, but I think it might have something to do with the way my scan chain was inserted.
The code I am trying to insert a scan chain into is:
module dff(CK, Q, D);
input CK, D;
output Q;
reg Q;
always@(posedge CK)
Q <= D;
endmodule
module s27(GND,VDD,CK,G0,G1,G17,G2,G3);
input GND,VDD,CK,G0,G1,G2,G3;
output G17;
wire G5,G10,G6,G11,G7,G13,G14,G8,G15,G12,G16,G9;
dff DFF_0(CK,G5,G10);
dff DFF_1(CK,G6,G11);
dff DFF_2(CK,G7,G13);
not NOT_0(G14,G0);
not NOT_1(G17,G11);
and AND2_0(G8,G14,G6);
or OR2_0(G15,G12,G8);
or OR2_1(G16,G3,G8);
nand NAND2_0(G9,G16,G15);
nor NOR2_0(G10,G14,G11);
nor NOR2_1(G11,G5,G9);
nor NOR2_2(G12,G1,G7);
nor NOR2_3(G13,G2,G12);
endmodule
And the steps I used to create the scan insertion are:
set_scan_configuration -style multiplexed_flip_flop
compile -scan
set_dft_signal -view existing_dft -type ScanClock -port CK timing[list 40 60]
create_test_protocol
dft_drc
set_scan_configureation -chain_count 1
preview_dft
insert_dft
write -format verilog -hierarchy -output s27_dft.v
write_test_protocol -out s27_dut.spf
After that I don't get any errors, but I do get this warning:
The multi-clock protocol requires that the strobe time be before a clock's pulse if it is used for transition fault testing. (TESTXG-56)
Do you have any ideas of something I should change or add in order to increase my fault coverage to an acceptable amount?
Any suggestions you have would be much appreciated.
Thank you!